The present invention relates to electronic circuits, and more particularly to an input circuit adapted to automatically detect relatively high voltages and operate at a native voltage level corresponding to a detected external voltage level.
An integrated circuit (IC) is often required to receive and sense input signals having higher voltage levels than a maximum native operating voltage. The native voltage level is also typically the power supply voltage level. For instance, with an IC designed for a 1.2 V supply, the inputs of internal circuits and transistors can only withstand a maximum of 1.2 V across transistor gates (i.e., across any gate oxide) without damage occurring from electrical overstress. Prior art often resorts to use of special gate constructs or voltage level shifting techniques to sense external input signals. These special techniques are used to keep the accompanying high voltage from reaching internal CMOS transistors. These techniques allow input signal voltage levels up to a maximum of two times VDD (i.e., 2.4 V may be input to a 1.2 V circuit). Any voltage higher than two times the power supply voltage requires a different (i.e., thicker) gate transistor requiring additional processing and a more expensive dual-gate, dual-power-supply CMOS process. For reference, conventional dual-gate, dual-power-supply CMOS ICs today operating at 1.2 V use 3.3 V-capable transistors and circuits to handle 3.3 V to 5 V input signals (which is even less than the two times guidelines for 3.3 V devices).
In addition to the capability of accommodating high-voltage input signals, an input circuit needs to sense the proper voltage levels for logic state 1 or “high” signaling level and a voltage level for logic state 0 or “low” signaling level corresponding to the input signal coming from a given external environment. For example, with a 1.2 V input signal, the circuit must register logic state 0 for input signals between 0.0-0.6 V and register logic state 1 for input voltage levels between 0.6 and 1.2 V. With a 3.3 V input signal, the circuit must register logic state 0 for input signal levels between 0 and 1.65 V and register logic state 1 for input signal levels between 1.65 and 3.3 V. Registering proper logic levels is even more challenging when high-level input levels range between the 1.2 V and 3.3 V regions.
What is needed is an input circuit capable of receiving operational signal levels at either a native supply voltage level or at an external signaling-voltage level that exceeds two times the native supply level. The input circuit needs to operate at these elevated external signaling-voltage levels and not have any input devices exposed to electrical overstress and oxide breakdown.